1. Field of the Invention
This invention relates to solid state electronics, in particular to a novel high frequency silicon based resonant tunnel diode with negative differential resistance.
2. Description of the Related Art
The tunnel diode formed by a heavily doped p-n junction was invented by Esaki in 1958. This diode operated on the basis of interband tunneling, wherein charge carriers moved between valence and conduction bands by tunneling through an intervening potential barrier. Subsequently, in 1974, Esaki and co-workers demonstrated a resonant tunneling diode (RTD) consisting of two potential barriers separated by a potential well using a III–V compound semiconductor (L. L Chang, L. Esaki, and R. Tsu, “Resonant tunneling in the semiconductor double barriers,” Appl. Phys. Lett., Vol. 24, pp. 593–595, June 1974). In this device, the tunneling was intraband, between conduction and conduction or valence and valence bands, through an intermediate quantum well whose bound state energies corresponded to those energies of injected electrons which would have the maximum probability for tunneling.
Over the past three decades, RTDs exhibiting negative differential resistance (NDR) have received a great deal of attention due to their potential for application in electronics. Since the RTD offers the capability of operation as an oscillator, an amplifier and a mixer at extremely high frequency and with high resonant current density and very low noise, its implementation in integrated circuits would minimize the total device counts, and standby current. Indeed, Noble (U.S. Pat. No. 6,208,555) provides an SRAM memory cell that includes two tunnel diodes coupled in series and a MOSFET. RTDs with good I–V characteristics have been demonstrated in heteroeptaxial systems such as GaAs/AlGaAs/GaAs (Dong-Joon Kim, Yong-Tae Moon, Keun-Man Song and Seong-Ju Park, “Effect of barrier thickness on the interface and optical properties of InGaN/GaN multiple quantum wells,” Jpn. J. Appl. Phys., Part 1, 40, 3085 (2001)) and SiGe/Si (U.S. Published Patent Application No. 2003/0049894) and will be briefly discussed below. In addition, Bate et al. (European Published Application No. 94107763.8, Publication No. 0 668 618 A2) discloses a resonant tunneling device in which a silicon well is sandwiched between epitaxially grown layers of CaF2.
Although RTDs have been known and used in demonstrating the operation of an oscillator, an amplifier and a mixer at extremely high frequencies and with high resonant current density and very low noise, while maintaining the minimum total device counts and standby current desirable in integrated circuit (IC) technology, they have been difficult to integrate into mainstream Si CMOS (Complementary Metal Oxide Semiconductor) IC technology.
In the RTD structure, the silicon film is sandwiched on each side by a SiO2 dielectric layer. The quantum barrier is made from this dielectric film, which has a relatively larger band gap than silicon. SiO2 is not the only material suitable for the barrier layer that has a wider band gap than silicon. The difference in the band gap between the silicon and its surrounding barrier layers results in a positive conduction band-offset (difference between the conduction band edge and barrier height) with respect to the smaller band gap of Si. The silicon layer between the two barriers, that has a width close to the electron's deBroglie wavelength, forms a quantum well that supports a band containing several discrete electron energy levels that may be broadened by various processes. The electron transport across the barrier occurs by means of this energy band (or bands), which, by its presence, promotes the tunneling of injected electrons and produces a corresponding tunneling current when an appropriate bias voltage is applied. When the band energy of the well is close to the conduction electron energy of the emitter electrode (the “resonance” referred to in the device name), the maximum tunneling current is produced. This current decreases as the conduction electron energy departs from the energy in the band due to the applied bias. This reduction in current as the voltage is increased gives rise to what is called the negative differential resistance (NDR) behavior in the I–V characteristics of the tunnel diode.
Although the SiO2 double barrier structure surrounding a silicon well was reported in H. Ikeda, M. Iwasaki, Y. Ishikawa, and M. Tabe, “Resonant tunneling characteristics in SiO2/Si double barrier structure in a wide range of applied voltage,” Applied Physics Letters, vol. 83, pp. 1456–1458, 2003, it remains a challenge for SiO2/Si/SiO2 type RTDs to find their way into applications. This is a result of their poor performance, which is due mainly to the large band offset between SiO2 and Si and the excessive thickness of the SiO2 of the buried oxide layer in a silicon-on-insulator (SOI) substrate. Okuno, in both (U.S. Pat. No. 5,466,949) and (U.S. Pat. No. 5,616,515) discloses a resonant tunneling diode formed by layering silicon dioxide barrier layers on either side of a germanium well, but, as already noted, this device structure is not compatible with silicon processing schemes.
Recently, new forms of bonding have provided a possible approach to the integration of RTDs with the backend copper interconnect technology commonly used in IC fabrications. This integration involves low temperature bonding techniques such as Cu—Cu thermocompression, and plasma bonding. The efficacy and detailed description of these and similar methods is described by Rafael Reif, Andy Fan, Kuan-Neng Chen and Shamik Das in “Fabrication Technologies for Three-Dimensional Integrated Circuits,” International Symposium on Quality Electronic Design, Mar. 18–21, 2002, San Jose, Calif., pp. 33–37. The type of integration demonstrated therein leads, in the present invention, to 3-D device and circuit architectures in which CMOS devices lie on the silicon plane, while RTD devices are placed at the interconnect level. As is pointed out by K. C. Saraswat, K. Banerjee, A. Joshi, P. Kalavade, S. J. Souri and V. Subramanian, in “3-D ICs with multiple Si layers: performance analysis and technology,” 197th Meeting of The Electrochemical Society, Toronto, May 2000, these techniques offer an effective use of the device area, while the replacement of lengthy horizontal interconnects by much shorter and more direct vertical interconnects leads to lower interconnect delays in overall circuit performance. Moreover, the 3-D integration with CMOS/BJT/SiGe (BJT being bi-polar junction technology) devices can lead to innovative circuit designs for future analog and digital circuit technologies, especially those involving SRAM and DRAM. By combining the advantages of 3-D architecture with the inherent fast tunneling properties of RTDs, an excellent emerging candidate for the next generation of nanoelectronic devices and circuits is produced.